The present invention relates to a method of manufacturing a semiconductor device and an apparatus for manufacturing the same. More particularly, the present invention relates to a method of forming a planarized dielectric layer for a semiconductor device and an apparatus for forming the same.
The planarizing of an interlayer dielectric formed between metal wiring layers or formed prior to a metallization process has become increasingly important as the semiconductor industry continues to manufacture semiconductor devices having higher packing densities and having conductive layers divided into a multitude of layers.
FIGS. 1A, 1B and 1C sequentially illustrate a process of forming and planarizing an interlayer dielectric according to a conventional method.
Referring to FIG.1A, a first dielectric 12 is formed on a semiconductor substrate 11. A conductive material of a relatively high melting point, e.g., polysilicon, poly+WSi or W, is then deposited and patterned thereon to form a conductive layer 13.
Referring to FIGS. 1B and 1C, a flowable insulating material such as borophosphosilicate glass (BPSG) is coated on the resultant structure, to thereby form a second dielectric layer 14. The second dielectric layer 14 is thermally treated at a temperature over 800.degree. C. so that the second dielectric layer 14 reflows. The reflow of the second dielectric 14 planarizes the surface thereof.
Such a conventional process for planarizing an interlayer dielectric has a disadvantage in that the reflow process requires a high temperature thermal treatment. This high temperature treatment destroys the junction of an impurity layer formed on the underlying semiconductor substrate 21.
FIGS. 2A, 2B, 2C and 2D sequentially illustrate a process of forming and planarizing a dielectric layer according to another conventional method.
Referring to FIG. 2A, a first dielectric layer 22 is formed on a semiconductor substrate 21. A conductive material of a relatively low melting point, such as aluminum, is coated on the first dielectric layer 22 and patterned to thereby form a conductive layer 23. The conductive layer 23 is a metal wiring layer.
Referring to FIG. 2B, an insulating material is coated on the resultant structure, to thereby form a second dielectric layer 24. The second dielectric layer 24 insulates the conductive layer 23.
Referring to FIGS. 2C and 2D, spin-on glass (SOG) 25 is coated on second dielectric layer 24 and etched back until the top portions of the second dielectric layer 24 over the conductive layer 23 is exposed, leaving SOG 25 only in recessed portions of the second dielectric layer 24 between the metal wiring of the conductive layer 23. Therefore, the metal wiring of the conductive layer 23 is planarized with the interlayer dielectric comprised of the second dielectric layer 24 and the layer of SOG 25.
The second conventional planarization process suffers from a disadvantage in that it involves complicated processes.
Dielectric materials such as an O.sub.3 -tetraethylorthosilicate (TEOS) or O.sub.3 -hexamethyldisiloxane (HMDS) oxide layer are now used expansively because these oxide materials exhibit far better conformality than does a more conventional oxide layer of silane (SiH.sub.4). The above mentioned dielectric materials have a surface dependence effect in which a deposition rate varies in accordance with the properties of the material of the underlying layer. The surface dependence effect hinders the control of the formation of the dielectric material layer to a uniform thickness, according to the properties of the underlying material layer. The surface dependence effect also lowers the deposition rate and gives the dielectric layer a porous film structure. These problems degrade the quality of the dielectric layer.
A O.sub.3 -TEOS oxide layer has the surface dependence effect during growth when the material of the underlayer is made of silicon, BPSG or aluminum (see Nishimoto et al., "A Preview for the Fiftieth Scientific Lectures" Applied Physics Society, 1989, 30a-D-3, p. 673).
Japanese Laid-open Patent Publication No. Hei 1-206631 suggests a method of depositing a plasma-TEOS oxide layer or plasma-SiH.sub.4 oxide layer on the overall surface of the underlying material prior to forming the O.sub.3 -TEOS oxide layer in order to reduce the surface dependence effect thereof.
The effect in which a deposition rate varies according to the property of the underlying material is believed to vary depending on whether the underlying material is hydrophilic or hydrophobic. However, this speculation does not explain the phenomenon in which the deposition rate of the O.sub.3 -TEOS oxide layer varies with the density of the wiring of an underlying conductive layer. FIGS. 3A, 3B, 3C and 3D are diagrams for explaining this phenomenon.
FIG. 3A illustrates a conductive layer. A first pad 42 is connected to a fine metal wire 41 of the conductive layer, and a second pad 43 of the conductive layer is not connected thereto. FIGS. 3B and 3C show that the dielectric material formed on the conductive layer shown in FIG. 3A results in different deposition characteristics between the dielectric layer formed on the first pad 42 and that formed on the second pad 43.
FIG. 3B illustrates the deposition of an O.sub.3 TEOS oxide layer 45 formed on the first pad 42 of the conductive layer, which is connected to the fine metal wire 41. A plasma-oxide layer 44 is deposited on the surface of the first pad 42 formed on a dielectric layer 40 formed of BPSG. An O.sub.3 -TEOS oxide layer 45 is formed thereafter over the resultant structure. FIG. 3B shows that the O.sub.3 -TEOS oxide layer forms peaks 45a along the edges of the underlying first pad 42.
FIG. 3C illustrates the deposition of an O.sub.3 -TEOS oxide layer 45 formed on the second pad 43 of the conductive layer, which is not connected to the fine metal wire 41. The O.sub.3 -TEOS oxide layer formed on the second pad 43 produces a peak 45b which is much smaller than the peak 45a produced on the first pad 42. It is believed that this is due to the fact that, as shown in FIG. 3A, electric charge distributions on the pads vary depending upon whether or not it is connected to the metal wire 41. The interaction (repulsion) between electric charges of adjacent metal wires 41 causes the electric charge variations. Therefore, the shape of the O.sub.3 -TEOS oxide layer formed on the first and second pads 42, 43 varies.
FIG. 3D shows the electrical field which is formed due to the electric charge distribution of the first pad 42, which is connected to the fine metal wire 41. The interaction between the electric charges of a plurality of fine metal wires 41 becomes stronger as the line spacing between the fine metal wires 41 becomes narrower. Thus, the amount of charges accumulated on the first pad 41 increases. Accordingly, the strength of the electrical field surrounding the first pad 42 increases. Therefore, the phenomenon of the variation of the deposition rate in accordance with the density of an underlying metal wire may be explained as being related to the electric charge distribution of the metal wire.
The cause of this phenomenon was closely examined. The kind and amount of charges conducted on the surface of the underlying material were varied with a deposition of an O.sub.3 -TEOS oxide layer. For this experiment, the O.sub.3 -TEOS oxide layer was deposited after B ions (trivalent) and P ions (pentavalent) were implanted on the silicon wafer in different amounts and energies.
FIG. 4 is a graph showing that the deposition rate of the O.sub.3 -TEOS oxide layer varied with the electrical polarity of the surface of the underlying layer.
Referring to FIG. 4, if B ions are implanted, the deposition rate of the O.sub.3 -TEOS oxide layer is high in any case, as compared with when no ions are implanted. On the other hand, if P ions are implanted, the deposition rate of the O.sub.3 -TEOS oxide layer is lowered as the ion implantation amount increases, and the deposition rate increases with greater ion energy levels.
An analysis of these results shows that, when positive charges (such as B ions) are produced on the silicon wafer, the deposition rate of the oxide layer is raised. However, when negative charges (such as P ions) are produced, the deposition rate of the oxide layer is lowered. Therefore, the deposition rate of the O.sub.3 -TEOS oxide layer varies with the strength and the electrical polarity of the surface of the underlying layer.
This analysis explains the variation of the deposition form of the oxide layer with the density of the underlying metal wiring. The higher energy levels result in a higher deposition rate because the P ions are implanted more deeply and away from the surface of the wafer, so that the ion implantation effect is weakened.
An improvement of the above-mentioned Japanese patent publication has been suggested wherein a dielectric is formed between metal wires (see Kurt Kwok et al., VMIC, Jun. 8 and 9, 1993, p.142). In an attempt to overcome the surface dependence effect, this method proposes that a plasma-enhanced chemical vapor deposition (PECVD) oxide layer be formed on a conductive layer of aluminum. The surface of the PECVD oxide layer is plasma-treated with nitrogen (N.sub.2), argon or hydrogen (H.sub.2) gas, and then the O.sub.3 -TEOS oxide layer is deposited thereon. The plasma treatment produces an abundance of positive ions on the surface of the underlying PECVD oxide layer, and the O.sub.3 -TEOS gas phase mixture has a lot of oxygen atoms which hold negative charges so that the positive ions and negative ions exhibit the electrical attraction therebetween. FIGS. 5A-5D sequentially illustrate the conventional process of forming a dielectric between metal wires proposed by Kurt Kwok et al.
Referring to FIGS. 5A-5D, a first dielectric layer 28 is formed on a semiconductor substrate 27. A conductive material having a relatively low melting point, such as aluminum, is coated on the first dielectric layer 28 and patterned so as to form a conductive layer 29. A PECVD oxide material is coated on the resultant structure, thereby forming a second dielectric layer 30. The surface of the second dielectric layer 30 is plasma-treated with N.sub.2, argon or H.sub.2 gas. An O.sub.3 -TEOS oxide layer is coated on the resultant structure, to thereby form a third dielectric layer 31.
The results of the method proposed by Kurt Kwok et al. conform with the experimental result and theories explained above, i.e. the surface dependence effect of the O.sub.3 -TEOS oxide layer is related to the electrical polarity of the underlying layer. However, since the PECVD oxide layer must be formed on the conductive layer, the method proposed by Kurt Kwok et al. involves a complicated process without any guarantee of the planarization of the surface of the formed dielectric layer.
The present invention contemplates a surface dependence effect of a dielectric layer in an organic relationship with the conductive layer. With such contemplation and realization, the problems associated with the conventional methods and apparatus' is overcome by a simplified process and planarization.